Integrated circuits (ICs) frequently include circuits that operate at different power high levels. For example, input/output (I/O) circuits frequently operate at a higher voltage than circuits in the interior (core) of the I/C. A higher voltage can be desirable at the I/O pads, for example, to interface properly with other ICs operating at a higher voltage, and to drive the heavily loaded output signals at an acceptable speed. A lower voltage can be desirable in the core of the IC, for example, to reduce power consumption and to enable the use of smaller transistors, thereby reducing the overall die size.
As another example, in some ICs a higher voltage level is sometimes applied to some circuits in the core. For example, to program non-volatile memories such as programmable read-only memories (PROMs) in a programmable logic device (PLD), a much higher voltage is applied to the memory cells than is used during user operation of the same PLD.
Another situation where different voltage levels can advantageously be applied is during the power-up process in some programmable logic devices (PLDS) or other ICs. During power-up, the power level can be too low for an IC to properly reset itself. For example, in a PLD including non-volatile memory cells, such as a complex programmable logic device (CPLD), some of the memory cells might supply an incorrect value after power-up. One method of correcting this potential problem is to pump the internal power supply to a higher value during the power-up process. In other words, during power-up the power high voltage externally applied to the IC is pumped up internally to a higher value.
Thus, many situations exist where an IC includes signals that are generated by a circuit at a first power high level, then provided to another circuit operating at a higher or lower power high level. To accommodate these situations, level shifter circuits are commonly used.
FIG. 1 shows a first well-known level shifter circuit that receives an input signal IN having a lower power level Lo-V, and provides an output signal OUT having a higher power level Hi-V. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.)
The level shifter circuit of FIG. 1 includes three P-channel transistors P1-P3 and three N-channel transistors N1-N3. Transistor P1 is coupled between power high level Hi-V and node OUTB, and has a gate terminal coupled to node OUT. Transistor N1 is coupled between node OUTB and ground GND, and has a gate terminal coupled to receive the input signal IN. Transistor P2 is coupled between a higher power level Hi-V and node OUT, and has a gate terminal coupled to node OUTB. Transistor N2 is coupled between node OUT and ground GND, and has a gate terminal coupled to receive a signal INB. Signal INB is provided by inverting signal IN using an inverter that includes transistors P3 and N3 coupled between a lower power level Lo-V and ground GND.
In the level shifter circuit shown in FIG. 1, transistors P1, P2, N1, and N2 are typically manufactured using a thicker oxide layer than transistors P3 and N3. This thicker oxide layer allows transistors P1, P2, N1, and N2 to withstand the higher power level Hi-V. Transistors P3 and N3 are typically manufactured using a thinner oxide layer that can withstand the lower power level Lo-V, but cannot withstand the higher power level Hi-V.
The level shifter circuit of FIG. 1 operates as follows. When the input signal IN is low (0 volts), transistor N1 is off and transistor N2 is on. Because transistor N2 is on, node OUT is low. Therefore, transistor P1 is on and node OUTB is high (Hi-V). Thus, transistor P2 is off.
When the input signal IN is high (Lo-V), transistor N1 is on and transistor N2 is off. Because transistor N1 is on, node OUTB is low. Therefore, transistor P2 is on and node OUT is high (Hi-V). Thus, transistor P1 is off.
Clearly, there is no undesirable current flow when the input signal IN is steady-state high or low. However, problems can arise when input signal IN changes state. When input signal IN changes state, there is a period when the circuit attempts to pull output nodes OUT and OUTB both up and down, i.e., both the N-channel and P-channel transistors attached to each node are turned on. This contention not only causes an undesirable crowbar current (increasing the power consumption of the IC), but also results in slower operation of the circuit. (The term “output node” as used herein does not necessarily imply that a signal on the referenced node is provided to a destination outside the circuit. However, when a node is designated as an output node, the node can generally be used to supply such a signal, if desired. Some nodes not designated as output nodes might also be able to supply an output signal.)
For example, consider the case when input signal IN changes from a low value to a high value. Initially, when input signal IN is low, signal INB is high, node OUT is low, and node OUTB is high. When signal IN goes high, transistors N1 and P1 are both on, and transistor N1 has to fight with transistor P1 to pull down node OUTB. Eventually, the voltage at node OUTB is low enough that transistor P2 begins to turn on. At this point, transistors P2 and N2 are both on. Transistor N2 eventually turns off as signal INB goes low, allowing partially-on transistor P2 to pull node OUT higher. Eventually, node OUT is finally high enough to fully turn off transistor P1, and the contention at node OUTB is resolved with a fully low value (GND) at node OUTB. Once node OUTB reaches a fully low value, transistor P2 turns fully on and node OUT is pulled completely high (Hi-V).
Because of the contention during the switching of input signal IN, it can be desirable to use larger-than-minimum sizes for the transistors in the level shifter circuit of FIG. 1. This further reduces the speed at which the circuit can operate.
Instead of (or in addition to) using larger transistors to improve the pull-up performance of the level shifter circuit, some circuit designers have inserted additional P-channel devices to improve the pull-up speed, as shown in FIG. 2. The circuit of FIG. 2 is similar to that of FIG. 1, except two new P-channel transistors (P4 and P5) are added. Transistor P4 is added between transistor N1 and node OUTB, and is gated by signal IN. Transistor P5 is added between transistor N2 and node OUT, and is gated by signal INB. Transistor P1 is now gated by node A, which lies between transistors N2 and P5. Transistor P2 is now gated by node B, which lies between transistors N1 and P4.
Transistors P4 and P5 are typically weak P-channel high voltage transistors. Because of this weakness, when signal IN changes from a low value to a high value, and transistor N1 turns on, new transistor P4 temporarily acts as a resistor and allows node B to go low faster than node OUTB. Thus, transistor P2 turns on faster than in the circuit of FIG. 1, allowing node OUT to go high more quickly. Thus, the contention on the output node OUT is more quickly resolved. Similarly, new transistor P5 allows node A to be pulled low more quickly, turning on transistor P1 more quickly when node OUTB is going high (i.e., after input signal IN goes low).
However, the drawback to this solution is that the only way to pull node OUT low is through weak transistor P5. Therefore, when input signal IN goes low and node OUT is pulled low, the transition is slower than in the circuit of FIG. 1. Similarly, when input signal IN goes high and node OUTB is pulled low, this transition is also slowed by the addition of transistor P4 to the pull-down path.
Crowbar current is often a serious consideration in the design of integrated circuits. Crowbar current can be particularly significant in level shifter circuits, which are frequently used to drive heavily loaded output pads. When many output signals change state concurrently, as is often the case, what can be a relatively unimportant crowbar current in one level shifter circuit is multiplied until it becomes a significant issue.
Therefore, it is desirable to provide level shifter circuits that allow for rapid transitions in the output values, preferably in both directions (low-to-high and high-to-low). It is further desirable to provide level shifter circuits that minimize the crowbar current during these transitions. It is further desirable to provide level shifter circuits that reduce or eliminate crowbar current during the power-up process.